Thursday, November 8, 2012

Sixth Generation VP8 Hardware Accelerators Released

Today we’re launching the G1 decoder “Fairway” and the H1 encoder “Foxtail”, the sixth generation VP8 hardware IP cores.

By redesigning the DMA engine architecture in the Fairway decoder we’ve improved VP8 decoding speed by 50% in a typical network-on-chip environment that exposes IP cores to very long memory latencies. Fairway is also using 20% less SRAM than the previous releases making the chip manufacturing cheaper.
Our target with the encoder was to further stretch the limits of single-pass, low-latency VP8 coding. The diagram below compares Foxtail to older IP encoder releases, as well as to the libvpx software VP8 encoder, configured to WebRTC quality settings. The results show that running a WebRTC session in a device with Foxtail VP8 encoding produces better quality video than libvpx across a wide range of datarates. 
We achieved the quality improvements in Foxtail by implementing macroblock adaptive rate-distortion optimization. Compared to the initial “Anthill” IP core release launched in March 2011, we’ve improved the compression rate by up to 40%.
The new releases, targeted for ASIC developers, are available at no cost by requesting a license at Integration support services and multi-standard versions are available from Verisilicon. The VP8 hardware cores have now been licensed to over 80 chip companies, and both the decoder and encoder are in mass production from a number of partners.
Looking forward, the hardware team will be focusing more attention on the next generation codec development including the VP8 experimental branch. 
Aki Kuusela is engineering manager for the WebM project hardware team.

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